Method of manufacturing semiconductor package

ABSTRACT

A method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a semiconductor chip and a connection region surrounding the mounting region, providing a semiconductor chip in the mounting region, the semiconductor chip including a connection pad provided on a top surface of the semiconductor chip, forming a protective layer covering a top surface of the substrate and the top surface of the semiconductor chip, forming a photosensitive insulating layer on the protective layer after forming the protective layer, patterning the photosensitive insulating layer thereby exposing the protective layer, removing the exposed protective layer, and forming a redistribution line to be electrically connected to the connection pad.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority under 35 U.S.C. § 119(a)to Korean Patent Application No. 10-2016-0135925, filed on Oct. 19,2016, in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to a method of manufacturing asemiconductor package, and more particularly, to a method ofmanufacturing a semiconductor package, which includes a process offorming a redistribution line.

According to recent technological development in the field of electronicdevices in line with users' demands, electronic devices are gettingsmaller and lighter, and semiconductor packages used in the electronicdevices are required to have high performance, and high capacity, whilehaving smaller size and lighter volume. To meet these demands, researchand development into fan-out panel level packages (FO-PLPs) and methodsof manufacturing the FO-PLPs have been increasing.

SUMMARY

The present disclosure provides a method of manufacturing asemiconductor package, whereby the semiconductor package may be formedto have high performance, high capacity, miniaturized size, and lightweight.

According to an aspect of the present disclosure, there is provided amethod of manufacturing a semiconductor package, the method including:providing a substrate including a mounting region having a recess spacefor accommodating a semiconductor chip and a connection regionsurrounding the mounting region; providing a semiconductor chip in themounting region, the semiconductor chip including a connection padformed on a top surface of the semiconductor chip; forming a protectivelayer covering a top surface of the substrate and the top surface of thesemiconductor chip; forming a photosensitive insulating layer on theprotective layer after forming the protective layer; patterning thephotosensitive insulating layer thereby exposing the protective layer;removing the exposed protective layer; and forming a redistribution lineto be electrically connected to the connection pad.

According to another aspect of the present disclosure, there is provideda method of manufacturing a semiconductor package, the method including:providing a substrate having a cavity region for accommodating asemiconductor chip and a ball-land region around the cavity region;mounting a first semiconductor chip in the cavity region; stacking asecond semiconductor chip on the first semiconductor chip in the cavityregion, the second semiconductor chip including a connection pad formedon a top surface of the second semiconductor chip; forming a protectivelayer covering a top surface of the substrate and the top surface of thesecond semiconductor chip; forming a photosensitive insulating layer onthe protective layer; patterning the photosensitive insulating layer toexpose the protective layer; forming a via hole by removing a residue ofthe photosensitive insulating layer while removing the exposedprotective layer; filling the via hole to form a redistribution line forelectrically connecting the connection pad to the ball-land region; andforming an external connection terminal electrically connected to theball-land region.

According to another aspect of the present disclosure, there is provideda method of manufacturing a semiconductor package, the method including:providing a substrate including a recess space for accommodating asemiconductor chip and a connection region surrounding the recess space;providing a semiconductor chip in the recess space, the semiconductorchip including a connection pad formed on a top surface of thesemiconductor chip; forming a protective layer covering a top surface ofthe substrate and the top surface of the semiconductor chip includingthe connection pad; coating a photosensitive insulating film on theprotective layer after forming the protective layer; irradiating lightto the photosensitive insulating layer to form a trench so that theprotective layer on the connection pad is exposed; removing the exposedprotective layer; and forming a redistribution line to be electricallyconnected to the connection pad.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will be more clearly understoodfrom the following detailed description taken in conjunction with theaccompanying drawings in which:

FIGS. 1 to 10 are cross-sectional views for explaining a method ofmanufacturing a semiconductor package, according to an exemplaryembodiment of the present disclosure, illustrated according to processorder;

FIGS. 11 to 14 are cross-sectional views of semiconductor packagesmanufactured by a method of manufacturing a semiconductor package,according to exemplary embodiments of the present disclosure; and

FIG. 15 is a schematic diagram of a configuration of a semiconductorpackage manufactured by a method of manufacturing a semiconductorpackage, according to an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION

The present disclosure now will be described more fully hereinafter withreference to the accompanying drawings, in which various embodiments areshown. The invention may, however, be embodied in many different formsand should not be construed as limited to the example embodiments setforth herein. These example embodiments are just that—examples—and manyimplementations and variations are possible that do not require thedetails provided herein. It should also be emphasized that thedisclosure provides details of alternative examples, but such listing ofalternatives is not exhaustive. Furthermore, any consistency of detailbetween various examples should not be interpreted as requiring suchdetail—it is impracticable to list every possible variation for everyfeature described herein. The language of the claims should bereferenced in determining the requirements of the invention.

In the drawings, like numbers refer to like elements throughout. Thoughthe different figures show various features of exemplary embodiments,these figures and their features are not necessarily intended to bemutually exclusive from each other. Rather, certain features depictedand described in a particular figure may also be implemented withembodiment(s) depicted in different figure(s), even if such acombination is not separately illustrated. Referencing suchfeatures/figures with different embodiment labels (e.g. “firstembodiment”) should not be interpreted as indicating certain features ofone embodiment are mutually exclusive of and are not intended to be usedwith another embodiment.

Unless the context indicates otherwise, the terms first, second, third,etc., are used as labels to distinguish one element, component, region,layer or section from another element, component, region, layer orsection (that may or may not be similar). Thus, a first element,component, region, layer or section discussed below in one section ofthe specification (or claim) may be referred to as a second element,component, region, layer or section in another section of thespecification (or another claim).

It will be understood that when an element is referred to as being“connected,” “coupled to” or “on” another element, it can be directlyconnected/coupled to/on the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, or as “contacting”or “in contact with” another element, there are no intervening elementspresent.

Embodiments may be illustrated herein with idealized views (althoughrelative sizes may be exaggerated for clarity). It will be appreciatedthat actual implementation may vary from these exemplary views dependingon manufacturing technologies and/or tolerances. Therefore, descriptionsof certain features using terms such as “same,” “equal,” and geometricdescriptions such as “planar,” “coplanar,” “cylindrical,” “square,”etc., as used herein when referring to orientation, layout, location,shapes, sizes, amounts, or other measures, encompass acceptablevariations from exact identicality, including nearly identical layout,location, shapes, sizes, amounts, or other measures within acceptablevariations that may occur, for example, due to manufacturing processes.The term “substantially” may be used herein to emphasize this meaning,unless the context or other statements indicate otherwise.

FIGS. 1 to 10 are cross-sectional views for explaining a method ofmanufacturing a semiconductor package, according to an exemplaryembodiment of the present disclosure, illustrated according to processorder. FIGS. 2 to 10 are cross-sectional views taken along a line X-X′of FIG. 1.

Referring to FIG. 1, a substrate 200 forming a semiconductor package 10(see FIG. 10) may include a mounting region 220 on which a semiconductorchip 100 (see FIG. 2) may be mounted, and a connection region 210surrounding the mounting region 220.

The substrate 200 may be, for example, a printed circuit board (PCB), aceramic substrate, a wafer for fabricating a package, or an interposer.

The mounting region 220 may be formed as an opening or a cavity. For theexample, the mounting region 220 may be formed to have an opening or arecess space in which the semiconductor chip 100 may be mounted (seeFIG. 2). The mounting region 220 may be formed in a portion of thesubstrate 200, for example, a central region, but the disclosure is notlimited thereto. For example, in some embodiments, the mounting region220 may be formed in a portion of the substrate 200 other than thecentral region. The mounting region 220 may be recessed from the topsurface of the substrate 200 to a predetermined depth or may be formedto be open. Dry etching, wet etching, screen printing, drill bit, laserdrilling, or the like may be used to recess or open the substrate 200.For example, the recess space of the mounting region of the substrate200 may include an opening or a cavity in which the semiconductor chip100 (see FIG. 2) may be accommodated. For example, in some embodiments,the semiconductor chip 100 may be placed in the mounting region 220which includes the opening or the cavity, and after placing thesemiconductor chip 100 in the mounting region 220, an encapsulant may befilled in a space between the mounting region 220 and the semiconductorchip 100 to mount the semiconductor chip 100 on the substrate 200. Insome embodiments, the semiconductor chip 100 may be placed in themounting region 220 which includes the opening or the cavity, and afterplacing the semiconductor chip 100 in the mounting region 220, anadhesive may be provided on the bottom surface of the semiconductor chip100 to mount the semiconductor chip 100 on the substrate 200.

The connection region 210 may include a top surface and a bottom surfaceand a single layer or multilayer interconnection pattern forelectrically connecting the top surface and the bottom surface of theconnection region 210. A conductive pad may be formed on the top surfaceand/or the bottom surface of the connection region 210. For example, anexternal connection terminal 610 electrically connected to theconductive pad on the top surface of the connection region 210 may beformed. The connection region 210 may be formed according to a balllayout defined in the international standard, regardless of the size ofthe mounting region 220.

The various pads of a device described herein may be conductiveterminals connected to internal wiring of the device, and may transmitsignals and/or supply voltages between an internal wiring and/orinternal circuit of the device and an external source. For example, chippads of a semiconductor chip may electrically connect to and transmitsupply voltages and/or signals between an integrated circuit of thesemiconductor chip and a device to which the semiconductor chip isconnected. The various pads may be provided on or near an externalsurface of the device and may generally have a planar surface area(often larger than a corresponding surface area of the internal wiringto which they are connected) to promote connection to a furtherterminal, such as a bump or solder ball, and/or an external wiring.

As used herein, the semiconductor package 10 may refer to asemiconductor device having one or more chips stacked on a packagesubstrate. The semiconductor package 10 may also refer to a plurality ofstacked packages, such as a package-on-package device. The term“semiconductor device” may be used generally to refer to one of thesepackages, whether a single package or a package-on-package device, andmay also be used to refer to devices such as single semiconductor chips,e.g., formed on a die from a wafer.

For example, according to an embodiment of the present disclosure, evenif the size of the semiconductor chip 100 is reduced according to thedevelopment of semiconductor manufacturing technology, the reliabilityof the semiconductor package 10 may be secured by maintaining a constantball layout of the connection region 210 for the semiconductor chip 100to be packaged without being influenced by the chip size.

Referring to FIG. 2, the semiconductor chip 100 may be inserted into themounting region 220 so that the top surface of the semiconductor chip100, on which a connection pad 110 is formed, faces upward, and thus,the top surface of the semiconductor chip 100 may be aligned with thetop surface of the substrate 200.

The semiconductor chip 100 may be a logic chip or a memory chip. Thelogic chip may be, for example, a microprocessor, an analog device, or adigital signal processor. The memory chip may be a volatile memory chipsuch as dynamic random access memory (DRAM) or static random accessmemory (SRAM), or may be a non-volatile memory chip such as phase-changerandom access memory (PRAM), magnetoresistive random access memory(MRAM), ferroelectric random access memory (FeRAM), or resistive randomaccess memory (RRAM). In some embodiments, the semiconductor chip 100may be a high bandwidth memory (HBM) DRAM.

The size of the mounting region 220 may be greater than the size of thesemiconductor chip 100. In some embodiments, a certain gap is includedbetween the semiconductor chip 100 and the mounting region 220 of thesubstrate 200 so that an encapsulant 230 (see FIG. 3) may be inserted.The gap may be formed to the extent that the encapsulant 230 may beinserted.

The top surface of the semiconductor chip 100 may be aligned with thetop surface of the substrate 200. In some embodiments, the top surfaceof the semiconductor chip 100 may be aligned with the top surface of thesubstrate 200 so as to be coplanar with the top surface of the substrate200. Alternatively, the level of the top surface of the semiconductorchip 100 may be lower than the level of the top surface of the substrate200.

In some embodiments, the bottom surface of the semiconductor chip 100may be aligned with the bottom surface of the substrate 200 so as to becoplanar with the bottom surface of the substrate 200, depending on thethickness of the semiconductor chip 100 and the thickness of thesubstrate 200. Alternatively, the level of the bottom surface of thesemiconductor chip 100 may be higher than the level of the bottomsurface of the substrate 200.

Referring to FIG. 3, the encapsulant 230 is formed to fill a spacebetween the semiconductor chip 100 and the substrate 200 and cover thebottom surface of the semiconductor chip 100 and the bottom surface ofthe substrate 200.

In a process of filling the space with the encapsulant 230, siliconoxide (not shown) is first deposited to a predetermined thickness. Thetop surface of the semiconductor chip 100 and the top surface of thesubstrate 200 may be connected to each other by the silicon oxide byfilling a gap between the semiconductor chip 100 and the substrate 200.A portion of the space between the semiconductor chip 100 and thesubstrate 200, which is not filled with the silicon oxide, may be filledwith a polymer such as polyimide.

The encapsulant 230 may be integrated with the semiconductor chip 100and the substrate 200 by a molding process. The encapsulant 230 may befilled in the gap between the semiconductor chip 100 and the substrate200. The semiconductor chip 100 and the substrate 200 may be firmlyfixed as the encapsulant 230 is filled in the gap.

In some embodiments, the encapsulant 230 may completely cover the sidesand bottom surface of the semiconductor chip 100 to seal thesemiconductor chip 100. Such a process of sealing the semiconductor chip100 is referred to as an encapsulation process. For example, the bottomsurface of the semiconductor chip 100 may not be exposed to the outsideby the encapsulation process.

In some embodiments, the encapsulant 230 may be filled so that thebottom surface of the semiconductor chip 100 is exposed to the outside.For example, the encapsulant 230 may be filled at the same level as thebottom surface of the semiconductor chip 100 to minimize the height ofthe semiconductor package 10 (see FIG. 10). Alternatively, after thesides and bottom surface of the semiconductor chip 100 are completelycovered with the encapsulant 230, the encapsulant 230 may be polished sothat the bottom surface of the semiconductor chip 100 and the bottomsurface of the substrate 200 are exposed to the outside.

Referring to FIG. 4, a protective layer 310 is formed to cove the topsurface of the semiconductor chip 100 and the top surface of thesubstrate 200.

The protective layer 310 may include an insulating material, and may be,for example, a silicon oxide layer, a silicon nitride layer, or asilicon oxynitride layer. The protective layer 310 may include amaterial having excellent bonding properties with respect to thesemiconductor chip 100.

The silicon-based insulating layer, for example, the silicon oxidelayer, the silicon nitride layer, or the silicon oxynitride layer, hasexcellent insulation performance and is formed to reflect the shape of alower layer. The protective layer 310 may be formed depending on theshape of the top surface of the semiconductor chip 100 and the shape ofthe top surface of the substrate 200. The profile of the protectivelayer 310 may be substantially the same as or similar to the profile ofthe top surface of the semiconductor chip 100 and the profile of the topsurface of the substrate 200. Accordingly, the protective layer 310 maybe formed to evenly cover the top surface of the semiconductor chip 100and the top surface of the substrate 200. However, the shape of theprotective layer 310 may vary depending on materials to be used, processconditions, and subsequent processes.

The connection pad 110 may be electrically connected to a circuitportion of the semiconductor chip 100 to electrically connect thesemiconductor chip 100 to an external device. The connection pad 110 isa part for inputting/outputting an electrical signal to/from thesemiconductor chip 100, and a plurality of connection pads 110 may beprovided on the semiconductor chip 100. The connection pad 110 mayinclude a metal having comparatively low resistivity, such as aluminium(Al) or copper (Cu). Accordingly, the protective layer 310 may preventthe connection pad 110 from being exposed to the air, thereby preventingthe connection pad 110 from being oxidized.

According to an exemplary embodiment of the present disclosure, theprotective layer 310 may prevent a residue of a photosensitiveinsulating layer 410 (see FIG. 5) from remaining on the connection pad110 of the semiconductor chip 100, thereby improving electricalcharacteristics of the semiconductor package 10 (see FIG. 10). Detailswill be described later.

Referring to FIG. 5, the photosensitive insulating layer 410 is formedon the protective layer 310 to a predetermined thickness.

The photosensitive insulating layer 410 may include a polymeric resinmaterial, for example, photo-imageable dielectric (PID). The PID mayremain as an insulating layer, which is a component of the semiconductorpackage 10 (see FIG. 10), after an exposure process and an etchingprocess to be described later.

The photosensitive insulating layer 410 may be a positive type. Thepositive type is a type in which a region irradiated with light reacts.The photosensitive insulating layer 410 may be in the form of a film,but the present disclosure is not limited thereto. When thephotosensitive insulating layer 410 is in the form of a film, a rolllaminator may be used to form the photosensitive insulating layer 410 onthe protective layer 310. For example, the photosensitive insulatinglayer 410 in the form of a film may be coated on the protective layer310.

The bottom surface 410B of the photosensitive insulating layer 410 maybe coated with an adhesive to improve the adhesion to the protectivelayer 310. The adhesive may be an inorganic adhesive or a polymeradhesive. The polymer adhesive may be a thermosetting resin or athermoplastic resin, or may be of a hybrid type formed by mixing the twocomponents, i.e., a thermosetting resin and a thermoplastic resin.

A thickness 410T of the photosensitive insulating layer 410 in a firstdirection may be greater than a thickness 310T of the protective layer310 in the first direction. The thickness 310T of the protective layer310 may be minimized to protect the top surface of the connection pad110. The thickness 410T of the photosensitive insulating layer 410 maybe a thickness sufficient to form a trench 410H (see FIG. 6).

Referring to FIG. 6, the photosensitive insulating layer 410 isirradiated with light or laser to form the trench 410H.

A process of exposing the photosensitive insulating layer 410 to lightor laser may include a stage of etching the photosensitive insulatinglayer 410 and a stage of dissolving the photosensitive insulating layer410. Both stages may be performed at the same time.

When the photosensitive insulating layer 410 is irradiated with light orlaser, an upper portion of the photosensitive insulating layer 410 isetched and a lower portion of the photosensitive insulating layer 410 isdissolved. Specifically, since a depth at which light or laser may etchthe photosensitive insulating layer 410 is limited, the photosensitiveinsulating layer 410 may be etched to a predetermined depth, and anon-etched lower portion of the photosensitive insulating layer 410 isexposed to the light or laser and thus is dissolved. Since the stage ofetching the photosensitive insulating layer 410 and the stage ofdissolving the photosensitive insulating layer 410 are performed at thesame time (e.g., simultaneously), the photosensitive insulating layer410 may be continuously etched and dissolved by the same light or laser.For example, when the photosensitive insulating layer 410 is exposed tolight or laser, both etching and dissolution processes are performed.

As a result, by irradiating light or laser to the photosensitiveinsulating layer 410, the trench 410H is formed so that the protectivelayer 310 on the connection pad 110 is exposed. Using the photosensitiveinsulating layer 410, a desired pattern may be obtained without using aphotomask such as a photoresist.

FIG. 7A schematically shows a state in which a residue 410R of thephotosensitive insulating layer 410 remains on the top surface of theprotective layer 310 after the trench 410H is formed. FIG. 7B is ascanning electron microscope (SEM) photograph showing a state in whichthe residue 410R of the photosensitive insulating layer 410 remains onthe connection pad 110 (see FIG. 6) when the protective layer 310 is notformed.

In recent semiconductor devices, as a semiconductor chip size is reduceddue to miniaturization of process technology and the number ofinput/output terminals increases due to diversification of functions,pitches of connection pads are getting smaller and smaller. In addition,as the convergence of various functions accelerates, a technology forintegrating various devices into one semiconductor package is emerging.

A semiconductor package may be manufactured by a flip chip process usinga bumping technique for electrical connection between semiconductorchips or between a semiconductor chip and a substrate. In such a bumpingtechnique, the number of input/output terminals of the semiconductorpackage and the size of the semiconductor chip may be limited due to thelimitation of bump miniaturization.

For example, when the size of the semiconductor chip is reduced or thenumber of input/output terminals increases, there is a limitation inaccommodating a large number of solder balls, which are finalinput/output terminals, on the top surface of the semiconductor chip. Toovercome this shortcoming, the semiconductor package may have anembedded structure for mounting a semiconductor chip inside a substrateor a fan-out structure for arranging solder balls, which are finalinput/output terminals of the semiconductor chip, on the outercircumferential surface of the semiconductor chip. In particular, afan-out panel level package (FO-PLP), in which a substrate is arrangedon the outer circumferential surface of a semiconductor chip to form aredistribution line, and a method of manufacturing the FO-PLP have beencontinuously studied and developed.

In a process of manufacturing the FO-PLP, a photosensitive insulatinglayer such as PID may be used as an insulating layer for forming theredistribution line. As described above, the photosensitive insulatinglayer 410 may be in the form of a film and include an adhesive on thebottom surface 410B. However, it is difficult to completely remove theadhesive due to the characteristics of the constituent material thereof.Accordingly, if the adhesive remains as a residue on the top surface ofa connection pad, a contact resistance of the redistribution line mayincrease, and the electrical characteristics of the semiconductorpackage may deteriorate.

It is very difficult to completely remove the residue 410R of thephotosensitive insulating layer 410 even by using a general residueremoving process, for example, an ashing process, a plasma etchingprocess, a wet etching process, or a cleaning process.

Thus, according to an embodiment of the present disclosure, the residue410R of the photosensitive insulating layer 410 remains on the topsurface of the protective layer 310, not on the top surface of theconnection pad 110, so that the residue 410R and the protective layer310 are sequentially or simultaneously removed during a process ofetching the protective layer 310. Details of this process will bedescribed later.

Referring to FIG. 8, the residue 410R (see FIG. 7) of the photosensitiveinsulating layer 410 remaining on the exposed protective layer 310 andthe exposed protective layer 310 are removed.

In some embodiments, a process of removing the residue 410R of thephotosensitive insulating layer 410 and the exposed protective layer 310may be a process of removing the residue 410R of the photosensitiveinsulating layer 410 at the same time as removing the exposed protectivelayer 310.

In order to expose the connection pad 110, the protective layer 310,which includes an insulating material existing on the connection pad110, has to be removed. As described above, the residue 410R of thephotosensitive insulating layer 410 may be on the top surface of theexposed protective layer 310. The protective layer 310 may be removed bywet etching or dry etching. During a process of etching the protectivelayer 310, the residue 410R of the photosensitive insulating layer 410may be simultaneously removed.

In some embodiments, a process of removing the residue 410R of thephotosensitive insulating layer 410 and the exposed protective layer 310may include descumming the residue 410R from the photosensitiveinsulating layer 410 and etching the exposed protective layer 310, whichare sequentially performed.

First, a descum process is a process of removing the residue 410R fromthe photosensitive insulating layer 410 by using an oxygen plasmaetching process or the like. However, the residue 410R of thephotosensitive insulating layer 410 may not be completely removed evenif after the descum process is performed. In addition, if the protectivelayer 310 does not exist and the connection pad 110 is exposedimmediately, the connection pad 110 may be damaged by the oxygen plasmaetching process.

According to an embodiment of the present disclosure, such problems areaddressed. For example, even if the residue 410R of the photosensitiveinsulating layer 410 is not completely removed by the descum process,the residue 410R may be removed during the process of etching theprotective layer 310, and the connection pad 110 may not damaged by thedescum process.

After the descum process, the residue 410R of the photosensitiveinsulating layer 410 may be removed in the process of etching theexposed protective layer 310. The protective layer 310 may be removed bywet etching or dry etching.

A via hole 310H through which the connection pad 110 is exposed may beformed by removing the residue 410R of the photosensitive insulatinglayer 410 and the exposed protective layer 310. Then, a process ofcuring the photosensitive insulating layer 410 may be performed. Thecuring process is a process of hardening the photosensitive insulatinglayer 410 to maintain the shape of the photosensitive insulating layer410 in which the via hole 310H is formed. After the exposure process andthe etching process, since the photosensitive insulating layer 410 maybe difficult to maintain the shape thereof, the patterned shape of thevia hole 310H may be maintained by going through the curing process. Thecuring process may be performed at a specific temperature for a specifictime.

Referring to FIG. 9, a via 510 and a redistribution line 520 are formedin the photosensitive insulating layer 410.

In one embodiment, first, a seed layer (not shown) is formed on thephotosensitive insulating layer 410 so that the inner surface of the viahole 310H (see FIG. 8) is covered. In this case, both the top surface ofthe photosensitive insulating layer 410 and the inner surface of the viahole 310H may be covered with the seed layer. The seed layer may beformed by an electroless plating process (also referred to as a chemicalor auto-catalytic plating which is a non-galvanic plating method thatinvolves several simultaneous reactions in an aqueous solution, whichoccur without the use of external electrical power) or a sputteringprocess. Particularly, a process of forming the seed layer may be usedin forming the via 510 in the via hole 310H by using a plating process,and may be omitted according to a method of the formation of the via 510in the via hole 310H.

The process of forming the via 510 in the via hole 310H includes fillingthe inside of the via holes 310H with metal. The via 510 may includecopper (Cu), nickel (Ni), gold (Au), chrome (Cr), titanium (Ti),palladium (Pd), or an alloy thereof. The via 510 may be formed by aplating method, in which case a metal may be plated on the seed layer.In this case, the via 510 may be formed by electroplating. The via 510and the seed layer may include the same metal, for example, copper (Cu).

The redistribution line 520 may be formed on the top surface of the via510 and the top surface of the photosensitive insulation layer 410. Theredistribution line 520 may include the same metal as the via 510. Theredistribution line 520 may be formed by electroplating. For example, aredistribution layer may be plated on the seed layer. The redistributionline 520 is formed by patterning the redistribution layer by using anexposure process and an etching process. An insulating layer pattern 420may be formed between patterned redistribution lines 520. The insulatinglayer pattern 420 may include a silicon oxide layer, a silicon nitridelayer, a silicon oxynitride layer, or a PID.

In some embodiments, the via 510 and the redistribution lines 520 may besimultaneously formed through a damascene process. For example, after aconductive layer filling the inside of the via hole 310H and coveringthe top surface of the photosensitive insulating layer 410 is formed,the via 510 and the redistribution line 520 may be simultaneously formedby using an etching process such as etch-back.

Referring to FIG. 10, a redistribution via 530 and a redistribution pad540 are formed on the redistribution line 520 and an external connectionterminal 610 is formed on the redistribution pad 540 to complete thesemiconductor package 10.

A method of forming the redistribution via 530 and the redistributionpad 540 is similar to the process of forming the via 510 and theredistribution line 520, described above. A second photosensitiveinsulating layer 430 is formed on the redistribution line 520 and lightor laser is irradiated to the second photosensitive insulating layer 430to form a trench and expose the redistribution line 520. Subsequently,the redistribution via 530 and a redistribution pad layer are formed byperforming an electroplating process for filling the trench, and theredistribution pad layer is patterned to form the redistribution pad540.

The external connection terminal 610 may be electrically connected tothe redistribution pad 540. For example, the external connectionterminal 610 may be electrically connected to the connection pad 110.Through the external connection terminal 610, at least one of a controlsignal, a power supply signal, and a ground signal for the operation ofthe semiconductor chip 100 may be received from the outside (e.g.,outside of the semiconductor package 10), a data signal to be stored inthe semiconductor chip 100 may be received from the outside, or a datasignal stored in the semiconductor chip 100 may be provided to theoutside. For example, the external connection terminal 610 may have apillar structure and include a solder ball or a solder layer.

When the external connection terminal 610 is in the form of a solderball, the external connection terminal 610 may be formed into a ballshape by a surface tension effect after a reflow process. In someembodiments, a lead-free solder ball including tin (Sn) may be used asthe external connection terminal 610.

The surface of the redistribution pad 540 may be subjected to surfacetreatment such as organic coating or metal plating to prevent thesurface from being oxidized. For example, the organic coating may be anorganic solder preservation (OSP) coating and the metal plating may betreated with gold (Au), nickel (Ni), lead (Pb), or silver (Ag).

The external connection terminal 610 may be arranged above the substrate200 by forming the redistribution line 520. A position at which theexternal connection terminal 610 is formed may be different from theposition of the connection pad 110 of the semiconductor chip 100 due tothe redistribution line 520. For example, regardless of the size of thesemiconductor chip 100, the semiconductor package 10 may be manufacturedaccording to a ball layout defined in the international standard. Itshould be noted that although certain explanations herein describefeatures with respect to only one element (e.g., an external connectionterminal 610), it should be evident from the drawings that a pluralityof such elements are included in the various embodiments shown in thevarious figures.

Consequently, in the semiconductor package 10 manufactured by themanufacturing method according to one embodiment of the presentdisclosure, the protective layer 310 for protecting the connection pad110 of the semiconductor chip 100 is formed before the photosensitiveinsulating layer 410 is formed on the connection pad 110. Thus, theresidue 410R (see FIG. 7) of the photosensitive insulating layer 410does not remain on the connection pad 110, and thus, a contactresistance between the connection pad 110 and the via 510 may decrease,thereby improving the electrical characteristics of the semiconductorpackage 10.

FIGS. 11 to 14 are cross-sectional views of semiconductor packagesmanufactured by a semiconductor package manufacturing method accordingto exemplary embodiments of the present disclosure.

Referring to FIG. 11, a semiconductor package 20, in which asemiconductor chip 100 is mounted in a substrate 201 including a cavityregion 210C, is illustrated.

The semiconductor chip 100 in the semiconductor package 20 is mounted soas to be completely accommodated in the cavity region 210C of thesubstrate 201, and an adhesive member (not shown) may be formed on thebottom surface of the semiconductor chip 100 to fix the semiconductorchip 100 to the substrate 201.

In order to facilitate the mounting of the semiconductor chip 100, thesemiconductor chip 100 has a size slightly smaller than the size of thecavity region 210C. The top surface of the substrate 201 and the topsurface of the semiconductor chip 100 may be aligned on the same plane,and a space between the side surface of the semiconductor chip 100 andthe side surface of the cavity region 210C is filled with an encapsulant240.

A process of manufacturing the semiconductor package 20 is the same asor similar to the process of manufacturing the semiconductor package 10,described above with reference to FIGS. 1 to 10, except for a mountingregion of the semiconductor chip 100, and thus, detailed descriptionthereof will be omitted.

Referring to FIG. 12, a semiconductor package 30, in which an externalconnection terminal 610 is formed on the bottom surface of a substrate200, is illustrated.

In the semiconductor package 30, a semiconductor chip 100 is mounted ina substrate 200 having a mounting region and a connection region 210around the mounting region, in which a ball-land is formed, and aredistribution line 520 may be formed to form the external connectionterminal 610 on a surface opposite to a surface on which a connectionpad 110 is formed.

The connection region 210 in which the ball-land is formed is a regionin which an upper conductive pad 219, at which a via 510 is positioned,is positioned on an upper via 217 and overlaps the upper via 217 and alower conductive pad 211, at which the external connection terminal 610is positioned, is positioned under a lower via 213 and overlaps thelower via 213.

In more detail, the connection region 210 has a structure in which theupper conductive pad 219, an intermediate metal layer 215, and the lowerconductive pad 211 are sequentially stacked on an insulating member. Theupper conductive pad 219, the intermediate metal layer 215 and the lowerconductive pad 211 are electrically connected to each other by the uppervia 217 and the lower via 213. In addition, the upper conductive pad 219and the lower conductive pad 211 are each surrounded by an insulatingmember while exposing only connection portions. An exposed region of thelower conductive pad 211 is a region to which the external connectionterminal 610 such as a solder ball is attached after surface treatmentis performed, and an exposed region of the upper conductive pad 219corresponds to a ball-land to which the via 510 is electricallyconnected after surface treatment is performed.

The size of the via 510 may be smaller than the size of the externalconnection terminal 610. Accordingly, the exposed region of the upperconductive pad 219 may be smaller than the exposed region of the lowerconductive pad 211. The upper conductive pad 219 and the lowerconductive pad 211 may perform the same function even if the size of theexposed region of the upper conductive pad 219 and the size of theexposed region of the lower conductive pad 211 are different from eachother.

Although the substrate 200 in which a multilayer interconnection patternhaving three layers exists is illustrated in FIG. 12 by way of example,the multilayer interconnection pattern may have one, two, or four ormore layers as required.

The substrate 200 may be a printed circuit board (PCB) having asingle-layer or multilayer interconnection pattern therein. When thesubstrate 200 is the PCB, the PCB 200 may include a body layer, a lowerprotective layer, and an upper protective layer as a supportingsubstrate of the semiconductor chip 100. A single-layer or multilayerinterconnection pattern is formed in the PCB 200, and the upperconductive pad 219 in the PCB 200 may be electrically connected to theconnection pad 110 of the semiconductor chip 100 through the via 510 andthe redistribution line 520. The external connection terminal 610 may bearranged on the bottom surface of the PCB 200. The PCB 200 may bemounted while being electrically connected to a module substrate or asystem board through the external connection terminal 610.

A single-layer or multilayer interconnection pattern may be formed inthe body layer, and the external connection terminal 610 may beelectrically connected to the semiconductor chip 100 through theinterconnection pattern. The lower protective layer and the upperprotective layer serve to protect the body layer, and may include, forexample, a solder resist (not shown).

The body layer may be realized by compressing a polymer material such asa thermosetting resin, an epoxy resin such as flame retardant 4 (FR-4),bismaleimide triazine (BT) or ajinomoto build up film (ABF), or a phenolresin to a predetermined thickness so as to form a thin layer, forming acopper foil on both sides of the thin layer, and then forming aconductive pattern as a transmission path of an electrical signalthrough patterning. Also, conductive patterns formed on the bottom andtop surfaces of the body layer may be electrically connected to eachother through a via contact penetrating the body layer, and a solderresist may be coated on the entire lower and upper surfaces of the bodylayer, except for terminal connection portions, for example, the upperconductive pad 219 and the lower conductive pad 211, to implement alower protective layer and an upper protective layer.

The PCB 200 may be a single-layer PCB having interconnection lines ononly one side thereof or a double-layer PCB having interconnection lineson both sides thereof. Further, the PCB 200 may be implemented as amultilayer interconnection PCB by forming interconnection patternshaving three or more layers by using an insulator called a prepreg.

A process of manufacturing the semiconductor package 30 using theprinted circuit board 200 is the same as or similar to the process ofmanufacturing the semiconductor package 10, described above withreference to FIGS. 1 to 10, except for a position where the externalconnection terminal 610 is formed, and thus, detailed descriptionthereof will be omitted.

Referring to FIG. 13, a semiconductor package 40, in which a pluralityof semiconductor chips 101 and 102, i.e., first and second semiconductorchips 101 and 102, are mounted in a substrate 201 including a cavityregion 210C, is illustrated.

The first semiconductor chip 101 and the second semiconductor chip 102are stacked, and the first semiconductor chip 101 is positioned underthe second semiconductor chip 102. However, the present disclosure isnot limited thereto.

The plurality of semiconductor chips 101 and 102 in the semiconductorpackage 40 are mounted so as to be completely accommodated in the cavityregion 210C of the substrate 201, and an adhesive member (not shown) isformed on the bottom surface of the first semiconductor chip 101 to fixthe first semiconductor chip 101 to the substrate 201.

In order to facilitate the mounting of the plurality of semiconductorchips 101 and 102, the plurality of semiconductor chips 101 and 102 havesizes slightly smaller than the size of the cavity region 210C. The topsurface of the substrate 201 and the top surface of the secondsemiconductor chip 102 may be aligned on the same plane, and a spacebetween the side surfaces of the plurality of semiconductor chips 101and 102 and the side surface of the cavity region 210C is filled with anencapsulant 240. Although in the embodiment of FIG. 13, bothsemiconductor chips 101 and 102 are illustrated as having the samesizes, the disclosure is not limited thereto. In some embodiments, thesize of the semiconductor 101 may be different than the size of thesemiconductor chip 102.

The semiconductor package 40 may include the first semiconductor chip101 and the second semiconductor chip 102 stacked in a verticaldirection. The plurality of semiconductor chips 101 and 102 may beelectrically connected to each other through connection bumps 112. Inaddition, the plurality of semiconductor chips 101 and 102 may beattached to each other by a non-conductive film.

The plurality of semiconductor chips 101 and 102 may be a logic chip ora memory chip. For example, the plurality of semiconductor chips 101 and102 may all be memory chips of the same kind, or some of the pluralityof semiconductor chips 101 and 102 may be memory chips and others may bea logic chip.

Although the semiconductor package 40 in which the plurality ofsemiconductor chips 101 and 102 are stacked is exemplarily shown in FIG.13, the number of semiconductor chips that are stacked in thesemiconductor package 40 is not limited thereto. For example, three ormore semiconductor chips may be stacked in the semiconductor package 40.

The first semiconductor chip 101 may have a top surface and a bottomsurface. A connection pad 110 may be formed on the top surface of thefirst semiconductor chip 101. An adhesive member may be formed on thebottom surface of the first semiconductor chip 101.

The second semiconductor chip 102 may have a top surface and a bottomsurface. The second semiconductor chip 102 may include a lowerconnection pad 121 formed on the bottom surface of the secondsemiconductor chip 102 and an upper connection pad 125 formed on the topsurface of the second semiconductor chip 102. A through silicon via(TSV) 123 may penetrate the second semiconductor chip 102 and extendfrom the top surface of the second semiconductor chip 102 to the bottomsurface thereof, and may be connected to the lower connection pad 121and the upper connection pad 125.

The second semiconductor chip 102 may be mounted on the top surface ofthe first semiconductor chip 101. The second semiconductor chip 102 maybe electrically connected to the first semiconductor chip 101 throughthe connection bumps 112 interposed between the first semiconductor chip101 and the second semiconductor chip 102.

A process of manufacturing the semiconductor package 40 is the same asor similar to the process of manufacturing the semiconductor package 10,described above with reference to FIGS. 1 to 10, except for theplurality of semiconductor chips 101 and 102, and thus, detaileddescription thereof will be omitted.

Referring to FIG. 14, a semiconductor package 50, in which an externalconnection terminal 610 is formed on the bottom surface of a substrate201 and a plurality of semiconductor chips 101 and 102 are mounted in acavity region 210C, is illustrated.

In the semiconductor package 50, the plurality of semiconductor chips101 and 102 are mounted in a substrate 201 having the cavity region 210Cand a connection region 210 around the cavity region 210C, in which aball-land is formed, and a redistribution line 520 may be formed to formthe external connection terminal 610 on a surface opposite to a surfaceon which the redistribution line 520 is formed.

In some embodiments, a method of manufacturing a semiconductor packagemay include: providing a substrate including a recess space foraccommodating a semiconductor chip and a connection region surroundingthe recess region; providing a semiconductor chip in the recess region,the semiconductor chip including a connection pad formed on a topsurface of the semiconductor chip; forming a protective layer covering atop surface of the substrate and the top surface of the semiconductorchip including the connection pad; coating a photosensitive insulatingfilm on the protective layer after forming the protective layer;irradiating light to the photosensitive insulating layer to form atrench so that the protective layer on the connection pad is exposed;removing the exposed protective layer; and forming a redistribution lineto be electrically connected to the connection pad. The process ofirradiating light or laser to the photosensitive insulating layer mayinclude: etching an upper portion of the photosensitive insulating layerto a pre-determined depth and dissolving a non-etched lower portion ofthe photosensitive insulating layer at the same time by using same lightor laser.

A process of manufacturing the semiconductor package 50 is the same asor similar to the process of manufacturing the semiconductor package 10,described above with reference to FIGS. 1 to 10, except for the mountingposition of the external connection terminal 610 and the plurality ofsemiconductor chips 101 and 102, and thus, detailed description thereofwill be omitted.

FIG. 15 is a schematic diagram of a configuration of a semiconductorpackage 1000 manufactured by a method of manufacturing a semiconductorpackage, according to an exemplary embodiment of the present disclosure.

Referring to FIG. 15, the semiconductor package 1000 may include a microprocessing unit (MPU) 1010, a memory 1020, an interface 1030, a graphicsprocessing unit (GPU) 1040, functional blocks 1050, and a bus 1060connecting these elements.

The semiconductor package 1000 may include both the MPU 1010 and the GPU1040 or may include only one of the MPU 1010 and the GPU 1040.

The MPU 1010 may include a core and an L2 cache. For example, the MPU1010 may include multi-cores. The multi-cores may have the sameperformance as each other or different performances from each other.Also, the multi-cores may be simultaneously activated or may havedifferent activation time points.

The memory 1020 may store a result processed in the functional blocks1050 by control of the MPU 1010. The interface 1030 may exchangeinformation or signals with external apparatuses. The GPU 1040 mayperform graphic functions. For example, the GPU 1040 may perform videocodec or may process three-dimensional (3D) graphics. The functionalblocks 1050 may perform various functions. For example, when thesemiconductor package 1000 is an application processor (AP) used in amobile apparatus, some of the functional blocks 1050 may perform acommunication function.

The semiconductor package 1000 may include the semiconductor package 10,20, 30, 40, or 50 manufactured by a semiconductor package manufacturingmethod according to embodiments of the present disclosure, describedwith reference to FIGS. 10 to 14.

While the present disclosure has been particularly shown and describedwith reference to embodiments thereof, it will be understood thatvarious changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

What is claimed is:
 1. A method of manufacturing a semiconductorpackage, the method comprising: providing a substrate including amounting region having a recess space for accommodating a semiconductorchip and a connection region surrounding the mounting region; providinga semiconductor chip in the mounting region, the semiconductor chipincluding a connection pad formed on a top surface of the semiconductorchip; forming a protective layer covering a top surface of the substrateand the top surface of the semiconductor chip; forming a photosensitiveinsulating layer on the protective layer after forming the protectivelayer; patterning the photosensitive insulating layer thereby exposingthe protective layer; removing the exposed protective layer; and forminga redistribution line configured to be electrically connected to theconnection pad, wherein the protective layer comprises an insulatingmaterial, and a thickness of the protective layer is less than athickness of the photosensitive insulating layer, and wherein theprotective layer comprises a silicon oxide layer, a silicon nitridelayer, or a silicon oxynitride layer.
 2. The method of claim 1, whereinforming the photosensitive insulating layer comprises attaching, in aroll shape, a photosensitive insulating layer in a form of a film, inwhich a bottom surface has an adhesive property, onto the protectivelayer.
 3. The method of claim 1, wherein removing the exposed protectivelayer comprises removing a residue of the photosensitive insulatinglayer while removing the exposed protective layer.
 4. The method ofclaim 1, wherein removing the exposed protective layer comprises:descumming a residue of the photosensitive insulating layer; and etchingthe exposed protective layer.
 5. The method of claim 1, whereinproviding the semiconductor chip comprises aligning the top surface ofthe semiconductor chip with the top surface of the substrate so that thetop surface of the substrate and the top surface of the semiconductorchip are co-planar.
 6. The method of claim 1, wherein the recess spaceof the mounting region comprises an opening in which the semiconductorchip is accommodated.
 7. The method of claim 6, wherein providing thesemiconductor chip includes placing the semiconductor chip in themounting region, and further comprising, after placing the semiconductorchip in the mounting region, filling an encapsulant in a space betweenthe mounting region and the semiconductor chip.
 8. The method of claim1, further comprising: after forming the redistribution line, exposing aportion of the redistribution line to the outside of the semiconductorpackage and forming a redistribution pad; and forming an externalconnection terminal, electrically connected to the redistribution pad,above the connection region.
 9. The method of claim 1, wherein theremoving the exposed protective layer comprises: irradiating light tothe photosensitive insulating layer to form a trench so that theprotective layer on the connection pad is exposed; and dry etching orwet etching the exposed protective layer to remove the exposedprotective layer.
 10. A method of manufacturing a semiconductor package,the method comprising: providing a substrate having a cavity region foraccommodating a semiconductor chip and a ball-land region around thecavity region; providing a first semiconductor chip in the cavityregion; stacking a second semiconductor chip on the first semiconductorchip in the cavity region, the second semiconductor chip including aconnection pad provided on a top surface of the second semiconductorchip; forming a protective layer covering a top surface of the substrateand the top surface of the second semiconductor chip; forming aphotosensitive insulating layer on the protective layer after formingthe protective layer; patterning the photosensitive insulating layer toexpose the protective layer; forming a via hole by removing a residue ofthe photosensitive insulating layer while removing the exposedprotective layer; filling the via hole to form a redistribution line,wherein the redistribution line is configured to electrically connectthe connection pad to the ball-land region; and forming an externalconnection terminal electrically connected to the ball-land region,wherein the substrate comprises a printed circuit board including asingle-layer or multilayer interconnection pattern therein.
 11. Themethod of claim 10, wherein the second semiconductor chip comprises athrough silicon via (TSV).
 12. The method of claim 10, wherein theball-land region comprises a top ball-land formed on a top surface ofthe printed circuit board and a bottom ball-land formed on a bottomsurface of the printed circuit board, wherein the top ball-land and thebottom ball-land are electrically connected to each other through thesingle-layer or multilayer interconnection pattern and the externalconnection terminal is formed on the bottom ball-land.
 13. The method ofclaim 12, wherein forming the via hole comprises exposing the connectionpad and the top ball-land.
 14. The method of claim 10, wherein theremoving the exposed protective layer comprises: irradiating light tothe photosensitive insulating layer to form a trench so that theprotective layer on the connection pad is exposed; and dry etching orwet etching the exposed protective layer to remove the exposedprotective layer.
 15. A method of manufacturing a semiconductor package,the method comprising: providing a substrate including a recess regionfor accommodating a semiconductor chip and a connection regionsurrounding the recess region; providing a semiconductor chip in therecess region, the semiconductor chip including a connection pad formedon a top surface of the semiconductor chip; forming a protective layercovering a top surface of the substrate and the top surface of thesemiconductor chip including the connection pad; coating aphotosensitive insulating film on the protective layer after forming theprotective layer; irradiating light to the photosensitive insulatingfilm to form a trench so that the protective layer on the connection padis exposed; removing the exposed protective layer; and forming aredistribution line configured to be electrically connected to theconnection pad, wherein the protective layer comprises a silicon oxidelayer, a silicon nitride layer, or a silicon oxynitride layer.
 16. Themethod of claim 15, wherein irradiating light to the photosensitiveinsulating film comprises: etching an upper portion of thephotosensitive insulating film to a pre-determined depth; and dissolvinga non-etched lower portion of the photosensitive insulating film. 17.The method of claim 16, wherein both etching an upper portion anddissolving a non-etched lower portion are performed at the same time.18. The method of claim 15, wherein removing the exposed protectivelayer comprises removing a residue of the photosensitive insulating filmwhile removing the exposed protective layer.
 19. The method of claim 15,wherein the removing the exposed protective layer comprises dry etchingor wet etching the exposed protective layer.